Author: Johan Klockars (62.13.18.80)
Date: 12-09-2002 18:44
> We've looked it up, and found that the heavy part of mpeg-decoding could be implemented in the FPGA (called DCT - Descrete Cosine Transform). It's just that it would consume a little more than half of all the logical gates in the FPGA,
There is a lot of middle ground between having the FPGA do the entire IDCT and having the CPU do all of it. And for that matter between doing it all in parallel versus serially. The simplest possible general purpose CPU can do an IDCT, it just takes it a bit longer than it would a better one.
That is, it won't take any more hardware than you are willing to spend on it. Obviously, more hardware can be thrown at the problem, though, since it's easy to parallelize.
IIRC, an IDCT is mainly multiplies. In this case probably of the 8x8 bit sort.
A bit-serial or iterative 8x8 multiplier would hardly use any logic at all, and should easily run at 100+ MHz. A single one of those might beat the '060 at multiplications.
A fully pipelined ripple-carry multiplier would be larger (but still a small part of even the smallest Spartan-II FPGA), but probably easier to deal with and it would deliver a result per cycle.
Of course, a state machine will be needed to get data to and from the multiplier(s). I can't believe that would be anything major, though, considering that you already have the memory interface in there.
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