Author: Anders Eriksson (kryten.atari.org)
Date: 03-28-2003 19:18
Here's is a cut-paste of an english translation of Rodolphes recent long posting. It's snipped from the scene-bbs on www.dhs.nu:
"
I can now connect myself to the usent from the job....
Yesterday evening, late, I have resolved the problem on the SDRAM (I hope it was
the last).
SDR60 files were sent to Didier and it will make a test of perfs in Copy BACK!
There are 2 files SDR60. One which configures the controller in simpler
possible without the pagination management of the DIMM, and one which uses the pages
memoires opened and makes it possible to make PAGE HIT (less cycles for
access), very performents for the linear accesses (like some test
in Nembench).
On this subject, a software wrote to run on all TOS machine
(Z-Bench), I think Didier will use it. A small blow of
Gembench also to laugh, has so muh there tests which are badly
representatifs......
You realize : the 1st machine with one 060 which will use the Full
Copy BACK mode with the TOS!
The bench will be very high
This evening I test CT60-F30 connection to the logical analyzer to see what
happens on the DSP level and SCC interruption which are the 2 principal obscure
remaining points.
It should not take to much time considering the power of the tool which I have buy
now (and I do not regret the purchase, because for the continuation it will save
an insane time).
In fact they are DATA conections in general between CT and F30 which are
surely the causes, but the SDRAM being resolved I am relieved.
I will also pass SDMA accesses to the analysis to see what occurs with
the clock patch modification found on a lot of F30 with the 74F04 add on one
GAL.
According to whave this patch or not, the CT does not behave similar, proof
although the logic of connection in ABE is well too tight in timing term.
I will also control what occurs with the arbitration between the Blitter, SDMA and
CT, since Didier say to meseveral times odd tricks bound with interruptions (?).
Lastly, I will make verfication of all with the bus boost with 20 MHz instead of 16.
If all is OK, we will be able to deliver the 20 first cards to developers... for 1 or
2 weeks of tests before sends to the others.
Here is the program for the next days...
Exciting because it y will have discovers...
Thank you for your patience (only one person is desisted (German) the last
week = another one person which will be able to have a card).
A+
"
|
