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 Subject: RE: Even more nonsens... ;-)
Author: Shalroth (wwwcache-d.lmu.ac.uk)
Date:   11-15-2001 12:10

Okay.

The ARM-3 chip from Acorn.

64-way set-associative cache, and 6-stage instruction pipeline, dual execution units.

Shame it won't work in a TOS machine really, it's a damn fine CPU.

 Topics Author  Date
  ...And continues... new Flash 11-14-2001 05:07 
   Even more nonsens... ;-) new Flash 11-14-2001 07:32 
    RE: Even more nonsens... ;-) new Fat Rakoon 11-14-2001 19:37 
     RE: Even more nonsens... ;-) new Fredrik Olsson 11-15-2001 09:42 
      Now, THATīs no nonsens... ;-) new Flash 11-15-2001 16:54 
     RE: Even more nonsens... ;-) new Shalroth 11-15-2001 12:16 
     RE: Even more nonsens... ;-) new Elliot 11-17-2001 15:51 
      RE: Even more nonsens... ;-) new Flash 11-17-2001 22:32 
    RE: Even more nonsens... ;-)  Shalroth 11-15-2001 12:10 
   RE: ...And continues... new Scott 11-14-2001 16:14 

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