Author: Johan Klockars (as12-5-4.kp.g.bonet.se)
Date: 02-01-2002 00:43
> hmmm...I always thought a CISC at the same
> speed as a RISC with halfway comparable
> architecture must be a bit better because it
> features more commands.
Using the same technology, the RISC chip would normally be able to have a higher clock frequency, so comparing at the same frequency is irrelevant. To be able to run at the same clock frequency, the CISC would need more pipeline stages, which makes for a larger and more complicated chip, and also causes larger penalties for (mispredicted) branches.
There's no rule that says that RISC chips should have fewer actual instructions. They may very well have more, since the number of instructions is not a problem.
What they cut down on is the complexity of the instructions. For example, the RISC chip will not have any instructions that operate directly on memory (only load/store), it will not have complicated addressing modes (often just register indirect, possibly with a constant offset, sometimes with automatic increment/decrement), all it's instructions will (usually) have the same size, it is not likely to ever use more than two registers as source or have more than one destination register.
In the case of the '030 versus a decent RISC chip at the same clock frequency, the '030 should not stand a chance, for most things. The RISC chip would complete most instructions in a single clock cycle, while the '030 can't complete anything at all in less than two.
The ARM architecture has some neat features like being able to shift one of the operands of almost any instruction, and the ability to skip instructions depending on the current condition codes.
IIRC, none of the ARM processors has ever had an FPU, though.
> main reason for that RISCs are preferred
> nowadays is that those chips are smaller and
> can cycle faster.
Sort of true, but...
The Athlon and P4 currently hold the record clock frequencies among general purpose CPUs. Of course, both of them are really RISC chips at their core, and translate the x86 instructions on the fly (well, IIRC, the P4 actually caches the result of the translation).
The largest chips are probably some of the latest from IBM (Power4) or HP (PA), or maybe the Intel/HP Itanium. All RISC chips (though the Itanium is rather different).
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