Author: Flash (port311.cvx2-sto.ppp.netlink.se)
Date: 02-14-2002 00:06
Yep, there is something you could call a
controller, but I would prefer to call it,
-a multiplexer maybe? I just donīt understand
why they MUXes the buses when the CPU *has*
separate buses??? I was thinking about just
to remove the MUX controller, and hook my H/W
direct onto the buses, via some buffers...
The chip select is there anyway, so what do
you think? Silly, plain junk or just crazy? ;)
Could probably ruin the Quadra, but Iīm keen...
Anyway, I *finally* found out what causes the
absolute limit around 50-52MHZ! It wasnīt the
RAM or VRAM access time, it is the 88916 PLL
clockchip. Itīs rated 33/70, and I run it at
52/104. At more than 30 over the rating, the
clockpulses may not be too pretty anymore,
and the skew should be kinda ugly too...
I dug out a MC88915TFN133 instead, gonna swap
it tomorrow if I can spare a couple of hours.
Itīs rated 66.5/133, I think that should do it.
Moto says the skew at all six outputs is less
than 500ps when kept within the rated speed.
I wonder how much a 040 can be overclocked?
Heared any figures? Maybe time to call guinnes soon, hehe...
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