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 Subject: RE: expanding DSP SRAM
Author: Andrew W (
Date:   09-17-2002 21:17

It has been years since I've used the Motorola 56k, but this is what I remember off the top of my head...

The DSP56k has what's called a Harvard architecture (rather than a conventional, Von Neuman architecture?), which means that it has multiple memory busses. This is useful for DSPs, which generally require high-speed data throughput and very fast multiply-accumulate cycles. Internally, the chip actually has three separate 24-bit busses: X (X data), Y (Y data), and P (program). Externally these busses are mapped onto a single bus, and two extra pins, X/Y and P, are used by the DSP to signal which external memory map it's trying to access. These extra pins can be viewed as simply extra address pins - e.g., A16 and A17 - though in the case that P is asserted, X/Y is ignored.

Feel free to email me if you have any questions. I don't own a Falcon, so I don't normally peruse this discussion board. I'm happy to participate, however, if a discussion about the DSP takes off...

-andrew (andrew1_remote at hotmail - just remove the 1 from the username!)

 Topics Author  Date
  expanding DSP SRAM new redspctr 08-06-2002 01:14 
   RE: expanding DSP SRAM new Peter 08-06-2002 09:25 
    RE: expanding DSP SRAM new Peter 08-06-2002 15:19 
     RE: expanding DSP SRAM new redspctr 08-07-2002 02:50 
      RE: expanding DSP SRAM new Peter 08-07-2002 09:55 
       RE: expanding DSP SRAM  Andrew W 09-17-2002 21:17 

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